www.rfm.com e-mail: info@rfm.com page 1 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 ? 4.8designed for short-range wireless data communications ? supports rf data transmission rates up to 115.2 kbps ? 3 v, low current operation plus sleep mode ? up to 10 mw transmitter power the DR8000 hybrid transceiver module is ideal for short-range wireless data applications where robust operation, small size, low power consumption and lo w cost are required. the DR8000 utilizes rfm?s tr8000 amplifier-sequenced hybrid (ash) architec ture to achieve this unique blend of characteristics. all critical rf functions are contained in the hybrid, simplifying and speeding design-in. the receiver section of the DR8000 is sensitive and stable. a wide dynamic range log det ector, in combination with digital agc and a compound data slicer, provide robust performance in the pres ence of on-channel interference or noise. two stages of saw filtering provide excellent receiver out-of-band reje ction. the transmitter includes provisions for both on- off keyed (ook) and amplitude-shift keyed (ask) modulation. the transmitter employs saw filtering to suppress output harmonics, facilitating co mpliance with fcc and similar regulations. absolute maximum ratings rating value units power supply and all input/output pins -0.3 to +4.0 v non-operating case temperature -50 to +100 c soldering temperature (10 seconds, 5 cycles maximum) 260 c 916.50 mhz transceiver module DR8000 electrical characteristics characteristic sym notes minimum typical maximum units operating frequency f o 916.30 916.70 mhz data modulation type ook/ask ook data rate 30 kb/s ask data rate 115.2 kb/s receiver performance (ook @ 4.8kbps) sensitivity, 4.8 kbps, 10-3 ber, am test method -108 dbm input current, 4.8 kbps, 3.0v supply 4.2 ma sensitivity, 19.2 kbps, 10-3 ber, am test method -104 dbm input current, 19.2 kbps, 3.0v supply 4.25 ma transmitter performance (ook @ 4.8kbps) peak rf output power, 315 a txmod current p ol 10 dbm peak current, 315 a txmod current i tpl 32 ma ook turn on/turn off times t on /t off 12/6 s ask output rise/fall times t tr /t tf 1.1/1.1 s power supply voltage range (including i/o) vcc 2.2 3.7 vdc operating ambient temperature t a -40 +85 c power supply voltage ripple 10 mvp-p
www.rfm.com e-mail: info@rfm.com page 2 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 DR8000 pinout and dimensions 900 mils 1000 mils 1000 mils gnd - 1 pkdet - 2 rx bbo - 3 gnd - 4 rx- 5 t x - 6 lpfilt - 7 tx/rx - 8 ook/ask - 9 sleep - 10 20 - gnd 19 - vcc 18 - cfg clk 17- cfg data 16 - rx clk 15- 2g/3g mode 14- 4.8kbps/19.2kbps 13- gnd sc/dsss 12- gnd mode 11- gnd
www.rfm.com e-mail: info@rfm.com page 3 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 pin descriptions pin name in/out description 1,4,20 gnd - gnd is the ground pin. 19 vcc - vcc is a positive supply voltage pin. 2 pkdet out this pin is the peak detector output. a 0.022uf capacitor to ground (c5) sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. for most applications, these time constants should be coordi- nated with the base-band time constant . for a given base-band capacitor c bbo , the capacitor value c pkd is: c pkd = 2.0* c bbo , where c bbo and c pkd are in pf a 10% ceramic capacitor should be used at this pin. this time constant will vary between t pka and 1.5* t pka with variations in supply voltage, temperature, etc. t he capacitor is dr iven from a 200 ohm ?attack? source, and decays through a 200 k load. the peak detector is us ed to drive the ?db-below -peak? data slicer and the agc release function. the peak detector capacitor is discharged in the receiver power-down (sleep) mode and in the transmit modes. see the description of pin 3 below for further information. a 0.022uf capacitor is installed for operation at 4.8kbps. 3bbout out this pin is connected directly to the transceiver bbou t pin. this pin drives the cmpin pin through a coupling capacitor, c bbo = 0.01uf (c4), for internal data slicer operation at 4.8kbps. c bbo = 11.2*sp max , where sp max is the maximum signal pulse width in s and c bbo is in pf the nominal output impedance of this pin is 1 k.the bbout signal changes about 10 mv/db, with a peak-to- peak signal level of up to 450 mv. the signal at bbout is riding on a 1.5 vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. when an external data recovery process is used with agc, bb out must be coupled to the external data recovery process and cmpin by separate series coupling capacitor s. the output impedance of this pin becomes very high in sleep mode, preserving the charge on the coupling capacitor. the value of c3 on the circuit board has been chosen to match typical data encoding schemes at 4.8 kbps. if c4 is modified to support higher data rates and/or different data encoding schemes and pk det is being used, make the value of the peak detector capacitor c5 about 2x the value of c bbo . 5rxdata out rxdata is the receiver data output pin. it is a cmos output. the signal on this pin can come from one of two sources. the default source is directly from the output of the data slicer circuit. the alternate source is from the radio?s internal data and clock recovery circuit. when the internal data and clock recovery circuit is used, the signal on rxdata is switched from the output of t he data slicer to the output of the data and clock recov- ery circuit when a packet start symbol is detected. ea ch recovered data bit is then output on the rising edge of a rxdclk pulse (pin 16), and is stable for reading on the falling edge of the rxdclk pulse. 6 txmod in the transmitter rf output voltage is proportional to the input current to this pin. a resistor in series with the txmod input is normally used to adjust the peak trans mitter output. full transmitter power (10 mw) requires about 315 a of drive current. the transmitter output power p o for a 3 vdc supply voltage is approximately: po = 101*(i txm ) 2 , where po is in mw and the modulation current i txm is in ma the practical power control range is 10 to -50 dbm. a 5% txmod resistor value is recommended. internally, this pin is connected to the base of a bipolar transistor with a small emitter resistor. the voltage at the txmod input pin is about 0.87 volt with 315 ua of driv e current. this pin accepts analog modulation and can be driven with either logic level dat a pulses (unshaped) or shaped data pulses. a series 6.2 kilohm resistor is installed to provide +10dbm average output power with a +3vdc input. 7lpfadj in this pin is the receiver low-pass filter bandwidth adjust. the filter bandwidth is set by a resistor r lpf (r4) between this pin and ground. the resistor value can range fr om 510 k to 3 k, providing a filter 3 db bandwidth f lpf from 5 to 600 khz. the resistor value is determined by: r lpf = (0.0006*f lpf ) -1.069 where r lpf is in kilohms, and f lpf is in khz a 5% resistor should be used to set the filter bandwidth . this will provide a 3 db filter bandwidth between f lpf and 1.3* f lpf with variations in supply voltage, temperature, etc. the filter provides a three-pole, 0.05 degree equiripple phase response. a 470 kilohm resistor to gnd is installed to provide a 3db filter band- width of 5.275khz. connect an external 1%, 243kilohm resistor to gnd for 19.2kbps operation. 8tx/rx in logic input (cmos compatible). this pin, in 3g mode, selects the operation of the tr8000 . pull this pin ?high? for transmit mode. pull this pin ?low? for receive mode. do not allow this pin to float. 9 ook/ask in logic input (cmos compatible). this pin, in 3g mode, selects the operation of the tr8000. pull this pin ?high? for ook transmit/receive mode. pull this pin ?low? for ask transmit/receive mode. do not allow this pin to float.
www.rfm.com e-mail: info@rfm.com page 4 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 pin name in/out description 10 sleep in logic input (cmos compatible). this pin, in 3g mode, puts the tr8000 into sleep mode. pull this pin ?high? for sleep mode. pull this pin ?low? for operation mode. do not allow this pin to float. 11 sven in logic input (cmos compatible). this pin, in 3g mode, enables the start vector recognition circuit. the tr8000 will not output a recovered clock on rxdclk (pin 16) until the start vector, 0xe2e2, has been recog- nized. pull this pin ?high? to enable start vector recogni tion. pull this pin ?low? then ?high? to reset the start vector recognition circuit. do not allow this pin to float. 12 not used keep this pin pulled ?low?. 13 not used keep this pin pulled ?low?. 14 4.8kbps/ 19.2kbps in logic input (cmos compatible). this pin, in 3g mode, selects the receive data rate of the DR8000. pull this pin ?high? to select 4.8kbps. pull this pin ?low? to select 19.2kbps. do not allow this pin to float. note: operating at 19.2kbps will require the value of c4, c5 and r4 to change to accommodate the higher data rate. see the tr8000 datasheet for recommended component values. 15 3g sel in logic input (cmos compatible). this pin sets the processor to operate in 3g mode. the power-up operating configuration of the tr8000 device is controlled by the j2 jumper setting. when dc power is applied to the DR8000 with j2 installed across 2-3, this pin should be pu lled ?high? immediately after power-up to initiate 3g mode. failure to pull pin 15 ?high? after power-up will caus e the processor to remain inactive. pulling this pin ?high? wakes the processor for 3g mode operation. when dc power is applied to the DR8000 with j2 installed across 1-2, this pin should be held ?low? to operate in 2g mode. do not allow this pin to float. 16 rxdclk out rxdclk is the clock output from the data and clock reco very circuit. rxdclk is a cmos output. when the radio?s internal data and clock recovery circuit is not used, rxdclk is a steady low value. when the internal data and clock recovery is used, rxdclk is low until a packet start symbol is detected at the output of the data slicer. each bit following the start symbol is output at rxdata on the rising edge of a rxdclk pulse, and is stable for reading on the falling edge of the rxdclk pulse. once rxdclk is activated by the detec- tion of a start symbol, it remains active until sven (pin 11) is reset. see pin 11 description. 17 cfgdat in/out in 3g control mode, cfgdat is a bi-directional cmos l ogic pin. when cfg (pin 19) is set to a logic 1, con- figuration data can be clocked into or out of the radi o?s configuration registers through cfgdat using cfg- clk (pin 18). data clocked into cfgdat is transferred to a control register each time a group of 8 bits is received. pulses on cfgclk are used to clock confi guration data into and out of the radio through cfgdat. when writing through cfgdat, a data bit is clocked in to the radio on the rising edge of a cfgclk pulse. when reading through cfgdat, data is output on the rising edge of the cfgclk pulse and is stable for reading on the falling edge of the cfgclk. refer to the tr8000 datasheet for detailed timing. this pin is a high impedance input (cmos compatible) in 2g mode. this pin must be held at a logic level. do not allow this pin to float. 18 cfgclk in/out in 3g control mode, pulses on cfgclk are used to clo ck configuration data into and out of the radio through cfgdat (pin 17). when writing to cfgdat, a data bit is clocked into the radio on the rising edge of a cfg- clk pulse. when reading through cfgdat, data is stable for reading on the falling edge of the cfgclk. refer to the tr8000 datasheet for detailed timing. this pin is a high impedance input (cmos compatible) in 2g mode. do not allow this pin to float.
www.rfm.com e-mail: info@rfm.com page 5 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 theory of operation the DR8000 evaluation module is centered around the tr8000 ash transceiver. the DR8000 may operate in backward compatible 2g mode, or in the enhanced 3g mode. since 3g mode requires the use of a serial i/o port to configure internal registers, the module includes an on-board silicon labs c8051f330 microcontroller to control access to the serial port. when 2g mode is enabled the microcontroller serves no function. when 3g mode is enabled the microcontroller constantly scans pins 8-15 for a change of logic state. when a state change is detected on one or more of these pins, the microcontroller automatically updates the internal configuration registers via the serial port of the tr8000. the microcontroller assumes full control of the cfg pin, cfgclk pin, and cfgdat pin in 3g mode to continuously update the internal registers. the DR8000 module is designed to demonstrate the performance of the tr8000 ash transceiver at 4.8kbps, although other data rates are possible with changes in on-board component values. see pin descriptions and refer to the tr8000 datasheet. the DR8000 module may be mounted on a prototype assembly using standard 0.1? spacing, 10-pin headers spaced 0.9? apart. 2g mode operation the DR8000 may operate in 2g mode. see pin 15 description and power-up mode select (j2) section for mode select details. in 2g mode, the cfgclk pin (18) and cfgdat pin (17) operate as ctrl0 and ctrl1, respectively, just as for second-generation devices. the cfgclk and cfgdat pins are a high impedance input allowing external control for 2g configuration. the logic levels on cfgclk (ctrl0) and cfgdat (ctrl1) control the default 2g operation as shown below: current consumption monitor (j5) the current consumption of the tr8000 device may be monitored by removing j5 and connecting an ammeter across the terminals. when j5 is removed it isolates the tr8000 from vcc powering the on-board processor to give a true reading of the current consumption of only the tr8000 without the additional current usage of the processor. j5 must be installed to power the tr8000 if not using the header for current measurement. power-up mode select (j2) j2 is used to select the operating mode of the tr8000 device only at power-up. the state of j2 when vcc is applied will determine whether the board operates in 2g mode or 3g mode. pin 2 (center pin) of j2 is connected to pin 19 (cfg) of the tr8000 device and is grounded for 2g mode and functions as the chip select line for the serial interface in 3g mode. installing the jumper will either connect the cfg pin of the tr8000 to gnd or directly to the processor for control in 3g mode. see the table below for power-up jumper settings. after power-up if 3g mode is selected, pin 15 (3g sel) must be pulled ?high? to initiate the processor to operate in 3g mode. failure to pull pin 15 ?high? after power-up will cause the processor to remain inactive. programming header (j4) the programming header allows for custom firmware development for the silicon labs c8051f330 if desired. contact rfm for more information about custom firmware development. cfgclk (cntrl0) cfgdat (cntrl1) mode 0 0 sleep 1 0 tx ook 01tx ask 11rx j2 header j5 header setting power-up mode pin 19 j2(1-2) 2g connected to gnd j2(2-3) 3g connected to processor j4
www.rfm.com e-mail: info@rfm.com page 6 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 4.8kbps application circuit 4.8kbps application circuit 4.8kbps application circuit 4.8kbps application circuit 19.2kbps application circuit sample set ups 1=?pull high? 0=?pull low? *after data is received, reset this pin to ?0? then set back to ?1? to re-enable start vector recognition. command tx/rx (pin 8) ask/ook (pin 9) sleep (pin 10) sven (pin 11) dsss (pin 12) iss (pin 13) 4.8/19.2 (pin 14) 3g sel (pin 15) receive ook 4.8kbps 0 0 000011 receive ask 4.8kbps 0 1 000011 receive ask 19.2kbps (add ext 243k resistor on pin 7) 0 1 000001 receive ask 4.8kbps w/ start vector and clock recovery 0 1 01*0011 tx ook 1 0 000001 sleep 0 0 100000
www.rfm.com e-mail: info@rfm.com page 7 of 7 ?2008 by rf monolithics, inc. DR8000 - 4/8/08 note: specifications subject to change without notice. item reference description value qty 1 c2 capacitor smt 0603 27pf 1 2 c4 capacitor smt 0603 .01uf 1 3 c5 capacitor smt 0603 .022uf 1 4 c6 capacitor smt 0603 100pf 1 5 c7 capacitor smt 0603 0.1uf 1 6 c8 capacitor smt 0603 0.1uf 1 7 c9 capacitor smt 0603 0.1uf 1 8 c3 capacitor tantalum eia-b 4.7uf 1 9 l1 fair-rite bead 0603 2506033017yo 1 10 l2 inductor chip 0603 15nh 1 11 l3 inductor chip 0603 100nh 1 12 r1 resistor chip 0603 20k 1 13 r3 resistor chip 0603 100k 1 14 r4 resistor chip 0603 330k 1 15 r5 resistor chip 0603 6.2k 1 16 r6 resistor chip 0603 1.0k 1 17 r8 resistor chip 0603 1.0k 1 18 r7 resistor chip 0603 10k 1 19 u2 c8051f330 silicon labs microcontroller 1 20 u1 ic, tr8000 1 DR8000 bill of material (4.8kbps) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 rfio
|
